% To Open the Existing Model
open_system(‘Chaining_Diagram’)
Pos = [115, 88, 155, 122];
for i = 1:3
% To add a block to the model
h = add_block(‘simulink/Ports & Subsystems/Subsystem’, ‘Chaining_Diagram/Subsystem’, ‘MakeNameUnique’, ‘on’);
if i == 1
add_block(‘simulink/Sources/In1′,’Chaining_Diagram/Subsystem/In1′, ‘MakeNameUnique’, ‘on’);
add_block(‘simulink/Sinks/Out1′, ‘Chaining_Diagram/Subsystem/In1′, ‘MakeNameUnique’, ‘on’);
else
path = strcat(‘Chaining_Diagram/Subsystem’,num2str(i-1),’/In1′);
add_block(‘simulink/Sources/In1′, path, ‘MakeNameUnique’, ‘on’);
add_block(‘simulink/Sinks/Out1′, path, ‘MakeNameUnique’, ‘on’);
end
% To set the Dimension of the block
set_param(h, ‘Position’, Pos)
set_param(h, ‘ShowPortLabels’,'off’)
BlkName = strcat(‘disp(‘,num2str(i),’)');
set_param(h, ‘MaskDisplay’,BlkName)
set_param(h, ‘ShowName’,'off’)
set_param(h, ‘Mask’,'on’)
Pos = Pos + [0, 100, 0, 100];
end
add_line(‘Chaining_Diagram’,'Subsystem/1′,’Subsystem2/2′,’autorouting’,'on’)
add_line(‘Chaining_Diagram’,'Subsystem/2′,’Subsystem1/1′,’autorouting’,'on’)
add_line(‘Chaining_Diagram’,'Subsystem1/1′,’Subsystem2/1′,’autorouting’,'on’)
add_line(‘Chaining_Diagram’,'Subsystem1/2′,’Subsystem/2′,’autorouting’,'on’)
add_line(‘Chaining_Diagram’,'Subsystem2/1′,’Subsystem/1′,’autorouting’,'on’)
add_line(‘Chaining_Diagram’,'Subsystem2/2′,’Subsystem1/2′,’autorouting’,'on’)

% To save the open System
save_system(‘Chaining_Diagram’)

*******************************************
when this piece of code which i wrote is executed, connecting lines are getting overlapped. Any help to make it non Overlapping?
Thanks in advance

As I mentioned previously, I would like to better understand the issue. I am not sure what you mean by “to understand that the first 3 signals are indeed just one”. When looking at a bus creator block configured as you mention, It is possible to obtain the handle to the 4 input ports of the bus creator (using get_param(gcb,’PortHandles’)) and obtain their dimension from the CompiledPortDimensions property. In that case the first signal (the one created by a mux) has a dimension of 3 and the other ports a dimension of 1.

Maybe you could send me example model and script by email so that I could better understand what you are looking for and propose a more appropriate solution.

Finally, I apologize for not being clear, but the Vector Concatenate block would not add blocks to your model, it would replace the mux block.

Guy

Do you have any clue about that?

PS I’m trying to avoid add simulink blocks but extracting these data by command, this is why didn’t considerate the Vector Concatenate block.

Thank you.

angelo

I’m fighting with a problem involving what you described above and maybe you can suggest me some solution.
In the attempt of assign names by command to signals entering in a block (only by accident a bus creator) I’m not able to distinguish between 2 kind of signals. For example soppose you have these signals:
- a 3{3} signal created by a mux as you explained above
- three scalar signals (1 1 1)
So you have 4 signals (1+3) requiring to be named whereas counting them (for example by means of the CompiledPortDimensions parameter of the Inport of the bus creator) 6 signals (3+3) are tallied up.
Do you know any more parameter (or way) to understand that the first 3 signals are indeed just one (it correspond only one name to them)?

Thanks.

angelo