Comments on: A Better If-Else Construct

By: Guy Rouleau

Guy Rouleau — Mon, 16 May 2011 12:50:00 +0000

@rima, The Pulse Generator block takes different time steps when used with a variable step solver, versus fixed-step solver. This is why to see a different ouptut.

To avoid this change of behavior, I recommend following the guidelines provided in the Merge block documentation. Especially:

- Always use conditionally-executed subsystems to drive Merge blocks.

- Write your control logic to ensure that at most one of the driving conditionally-executed subsystems executes at any time step.

By: rima

rima — Mon, 16 May 2011 11:14:08 +0000

i am having problem using the merge block for a fixed step solver with sample time 0.1s. the problem is simple consisting of two pulse generator blocks and their o/p s are merged. the first pulse generator o/p a positive pulse of 0.5s pulse width & 0.1 amp after 10 s. the second pulse o/p a pulse of same pulse width but amp of -0.1 after 15s pulse delay. if i use a variable solver (ode45) the o/p of the merge block comes perfectly with consisting of a positive pulse followed by a negative pulse after 5 s. but if the solver is changed to fixed step solver (ode4 ) the o/p of the merge block is the negative pulse after 15s. the positive pulse disappears. i have change the pulse generator i/p to sample type with 0.1 s sample period then also the problem is not getting solved.

By: rima

rima — Mon, 16 May 2011 11:07:17 +0000

By: Gerry

Gerry — Thu, 11 Mar 2010 15:21:30 +0000

Guy, I wanted to thank you. I followed your instructions and “reset” the “output” with a specified value and that did the trick. I would have never thought to double-click the output field for more options.

Gerry

By: Guy

Guy — Wed, 10 Mar 2010 19:39:01 +0000

Hi Gerry – By double-clicking on the output port of the conditionnal subsystem, you can specify the “Output When Disabled” to be “reset” or “held”. If you set it to “reset”, the output will reset to the value specified in the “Initial Output” parameter when the condition is false. You can see an example of it in the demo model sldemo_ifsub.mdl.

Guy

By: Gerry

Gerry — Wed, 10 Mar 2010 18:58:53 +0000

Seth,

I’m having trouble with “if/then” subsystem you described above. I left a posted a message on Mathworks blog, yesterday, but gotten no responses. I believe my trouble is correct syntax. I believe it comes down to how to reset the “if/then” subsystem to false after it has been enabled the first time. Your thoughts will be very helpful.

Gerry

By: Bindu

Bindu — Fri, 30 Oct 2009 06:55:18 +0000

please tell me how can i get the sampling time used in simulation

By: Seth

Seth — Wed, 26 Aug 2009 04:33:06 +0000

@Bob – You got me thinking about this. I see what you mean about the number of wires and the challenge of making sure they get connected correctly every time. I hope I’ll be able to propose some kind of solution in a future post.

@valio – Start by rewriting the ODEs in terms of first order derivatives. This was discussed in a previous blog post about How to draw ODEs in Simulink.

By: valio

valio — Tue, 25 Aug 2009 17:48:35 +0000

Hello Seth!

Read all your good articles.

But can you please consider my question for your next article of just give me your kind shortly explanation.

Cant build simulink model for that ODE:

L1*x1′ + R1*x1 + M12*x2′ + 1/C1*int(x) = 0
L2*x2′ + R2*x2 + M21*x1′ = 0
where int(x1) = Uc

build model like this:

http://picspix.com/img87/5728/16333.jpg

but it was failed..

It’s classic quotation of LC circuit+mutal inductance bind

Thanks a lot, and
sorry for out of topic post.

Regards,
Valentino.

By: Bob

Bob — Thu, 20 Aug 2009 13:00:58 +0000

A topic that has caused great trouble over the years. As you mention, Simulink doesn’t always apply the conditional execution optimization (code that has states is a common reason here) and so it is generally required that developers use the If/Action or the Switch/Action (a great alternative to an If block with u1==0, u1==1, u1==2,…).

These always draw complaints about how many lines one needs to connect properly, how easy it is to make a mistake, and how hard it is to visually inspect. Most of the Action subsystems are more complex, with multiple inputs and outputs feeding multiple merge blocks and lines crossing everywhere.

To deal with this, I’ve seen:
- Put all the merge blocks in a merge subsystem to prevent lines crossing. Inside the merge subsystem, ports 1 & 3 feed the first merge block, ports 2 & 4 feed the second, or similar.
- Change the foreground color on the Action subsystem so the lines are colored and easier to trace.
- Use a virtual bus to bring all the signals together and then break apart without lines crossing.
- Use local From/Goto blocks to avoid crossing signals.

Some people also use the From/Goto to avoid having the dashed action lines crossing other lines on their way to that top port.

And because this is so messy, just the mechanics of implementing If/Then/Else logic gets dedicated to its own subsystem so it can be inspected independently. If the logic is complex, sometimes the If block gets its own subsystem (or Stateflow chart with Boolean outputs) too.

We encourage people to do something, but don’t have a standard. What do others do to create maintainable models as the Action subsystem I/O grows?