Ashish.

so i had build my own customized basic blocks which i did using the existing blocks.

everytime i need to change the size say 2 bit gate to 3 bit gate i have to go to the block replicate the existing logic.

Is there a way build a system which takes the bit size as input and then generates the required block … just like we vary the size of ordinary and gate.

basically i want to build a asynchronous library of my own. Where do i start ?

thanks for providing the example!

I was just wondering why the lines
model_YDim = model_XDim;
loop_ub = model_XDim - 1;
for (tmp = 0; tmp <= loop_ub; tmp++) {
Y[tmp] = 2.0 * X[tmp];
}

aren’t converted into
for (tmp = 0; tmp <= model_Xdim-1; tmp++) {
Y[tmp] = 2.0 * X[tmp];
}

This would be a special case of expression folding.

I was wondering if this optimisation was considered at design/is planned for implementation?

Han

If you send me a simplified example that demonstrates what you describe, I would be interested to give it a look and try to explain or find a workaround for this behavior.

Is there supposed to be subtle differences between ‘Minimize algebraic loop occurrences’ for atomic systems and model references. I have created a simple model which exhibits different behavior between the two (in both 2007b and 2009b). I am ultimately trying to determine if I can help Simulink resolve the generic algebraic loop case with model references for those systems which don’t actually have loops. This is for users who have little experience with the subtleties of model references.

My model is a simple loop of subsystems of a control system. The plant has no direct pass-through paths. Here are the two behaviors:

Atomic subsystems: Highlights the loop at update diagram time and does not allow simulation since update diagram fails. Setting ‘MALO’ on the block which is not direct pass-through caused the block order to change to make this block first and the algebraic loop is no longer detected. Viola. Changing the block order through ‘Priority’ also succeeds in clearing up the false loop detection.

Model references: Throws warnings about the false algebraic loop, but allows update diagram to complete. Simulation is possible, but the algebraic loop algorithm is occurring at each time step, slowing the simulation and causing additional IC headaches. Setting ‘MALO’ in the model which is not direct pass-through does nothing except throw additional ‘Unable to remove algebraic loops’ warnings. Block order remains unchanged and ‘Priority’ is also unable to change Simulink’s mind.

I can send you my example if you are interested.