{"id":2756,"date":"2011-04-29T13:21:17","date_gmt":"2011-04-29T13:21:17","guid":{"rendered":"https:\/\/blogs.mathworks.com\/pick\/2011\/04\/29\/mixing-analog-and-digital-signals\/"},"modified":"2016-05-17T21:20:30","modified_gmt":"2016-05-18T01:20:30","slug":"mixing-analog-and-digital-signals","status":"publish","type":"post","link":"https:\/\/blogs.mathworks.com\/pick\/2011\/04\/29\/mixing-analog-and-digital-signals\/","title":{"rendered":"Mixing Analog and Digital Signals"},"content":{"rendered":"
\r\n\r\nIdin<\/a>'s pick this week is Analog\/Mixed-Signal Examples<\/a> by Dick Benson<\/a>.\r\n\r\nHi, my name is Idin, and this is my first post for Pick of the Week as a guest blogger. My background is in wireless communications,\r\nand that's the area I support as an Applications Engineer at MathWorks. I started using MATLAB occasionally during my undergrad\r\ndays, but these days, I have MATLAB open on my desktop all the time. I mostly focus on Simulink and our tools for targeting\r\nwireless communication hardware.<\/i>\r\n\r\nCommunication systems (wired or wireless) are typically a complex mix of analog and digital components. Simulink is one of\r\na small set of simulators that can naturally simulate analog and digital components in the same system. Examples of such systems\r\ninclude phase-lock-loops (PLL<\/a>), clock data recovery (CDR<\/a>), and analog-to-digital converters (ADC<\/a>). Components that include both digital and analog portions are referred to as \"mixed-signal\".\r\n\r\nThis week's pick is a collection of examples created by my colleague, Dick Benson. It is an impressive set of 60+ Simulink\r\nmodels that include, among others, an interleaved ADC, clock multiplying delay lock loop, clock recovery for NRZ data, PLL,\r\nfractional N PLL, digital fractional N PLL, Sigma-Delta ADC, elliptic LC filter design, RF examples, numerous Circuit Level\r\nexamples such as switching power supplies, class D H bridge audio amp, active filters, passive filters, and simulated vector\r\nnetwork analyzers.\r\n\r\nWhat I like about these models is that they typically show how a simple system can be designed and simulated, and then go\r\non to show how real-world impairments and mitigation algorithms can be modeled. As such, they can be used to learn about both\r\nthe Simulink environment, and the theory behind the systems being modeled.\r\n\r\nThese models also include many reusable blocks that can complement the Simulink libraries for an analog\/mixed-signal designer.\r\nSome examples of these blocks are: VCO with user-defined phase noise, analog spectrum analyzer, transfer function estimator,\r\npeak-to-peak jitter measurement, and switched-capacitor circuits.\r\n\r\nLet's look at the set of models concerning PLLs.\r\n\r\nWe can start with the first model, Simple PLL, shown below:\r\n\r\n\"\"\r\n\r\nThis model shows a simple PLL structure that multiplies the reference 100MHz input frequency by a factor of 8 to produce an\r\n800MHz signal at the output of the VCO. If run as-is, the output spectrum look like the following:\r\n\r\n\"\"\r\n\r\nNote the purity of this tone (clear to at least 100dB). This models an ideal system. In a real system, the two D flip-flops\r\non the top left may not have identical switching characteristics (in fact, they almost certainly won't). To model this behavior,\r\nwe switch in the \"delay asymmetry\" block (block in red). This models a real impairment in the system, and we can see its effect\r\non the output:\r\n\r\n\"\"\r\n\r\nNote the two spurs at 100MHz away from our desired carrier (this is the frequency of the reference input signal).\r\n\r\nTo mitigate this impairment, we can introduce a low-pass filter on the VCO control voltage (change switch SW2 to the right),\r\nwhich results in the following output:\r\n\r\n\"\"\r\n\r\nYou can see that we have now filtered out the spurs at +\/-100MHz. However, we're still allowing some noise close to our desired\r\ncarrier. By making the filter more aggressive, we can eliminate more of this noise, but that will negatively affect our loop\r\nbandwidth (which relates to the loop's ability to acquire the initial phase lock, or to recover from losing its lock). This\r\nis the classic engineering trade-off: we desire a larger loop bandwidth, and less noise. A PLL designer can use a model like\r\nthis to determine how he\/she will make that trade-off.\r\n\r\nThe next three PLL models in this set show more sophisticated designs, which multiply the reference input frequency by a non-integer\r\nfactor (known as fractional-N PLLs). The two models with \"digital compensation\" highlight Simulink's ability to naturally\r\nintegrate digital and analog components, as well as practical techniques for producing a clean tone at the output (see the\r\nmodels for references).\r\n\r\nOverall, the PLL models can be useful whether you're an experienced PLL designer or if you\u2019re just trying to learn about PLLs.\r\nFor a beginner these models can serve as a tutorial, and because of the dynamic simulation capability, they can be used to\r\nshow how different choices affect the loop's behavior. For a PLL expert, these models show how the Simulink environment lends\r\nitself to simulating PLLs and studying the trade-offs that any designer will have to make. The models also provide a library\r\nof reusable components (especially for measurements) that can be used in any analog\/mixed-signal model.\r\n\r\nThis has been a great submission from Dick Benson who has 25+ years of experience in this field, and I encourage you to look\r\nat his other submissions for more great examples of how Simulink can be used for communication system simulations.\r\n\r\nAs always, we welcome your comments!<\/a>\r\n\r\n