Semiconductor Design and Verification

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Enhancing Mixed-Signal IC Design with Symbolic State-Space Models

 

In the world of Analog/Mixed-Signal Integrated Circuit (IC) design, transfer functions have long been the go-to method for representing and analyzing linear time-invariant (LTI) circuits. However, this traditional approach comes with its own set of limitations:

  • Single-Input-Single-Output (SISO) Limitation: Transfer functions are only applicable to SISO systems, leaving out the complexity of Multiple-Input-Multiple-Output (MIMO) systems.
  • Lack of Internal State Description: They do not describe internal system states, limiting the depth of analysis.

State-Space vs. Transfer Function and Symbolic vs. Numerical

To address these shortcomings, the state-space representation is often considered. However, it requires extensive manual calculations, which are time-consuming and error-prone, especially when circuit topologies change.

Moreover, both state-space models and transfer functions, when taken into their numerical form, can suffer from numerical truncations and potentially lead to ill-conditioned system representations.

 

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Auto-Generated Symbolic State-Space

The automatic generation of symbolic state-space models effectively overcomes these limitations effectively by providing:

  • Symbolic Nature: Allows for the introduction of numerical values later in the process, minimizing issues related to numerical truncations.
  • Automation: Eliminates the need for manual calculations, enhancing efficiency and reducing errors.

Symbolic representations offer other significant advantages, as they support advanced analytical methodologies, such as robust control techniques. These methodologies can often provide closed form results, in contrast to statistical outcomes typically produced by methods like Monte Carlo simulations.

 

More about Symbolic State-Space Generation

To delve deeper into the automatic extraction of symbolic state-space representations, refer to the paper titled “Automating the Use of State-Space Representations in Mixed-Signal IC Design and Verification” authored by Francesco Stilgenbauer from STMicroelectronics and other contributors that has been presented last October at DVCON Europe 2024.

I had the honor of co-authoring this paper and learned a great deal from Francesco.

 

Figure 1: Modified schematic of the differential audio LC filter taken as a case study in Francesco’s paper

Figure 1: Modified schematic of the differential audio LC filter taken as a case study in Francesco’s paper

 

Read the full paper on IEEEXplore

Leveraging MATLAB and Simulink Capabilities

Being based on MATLAB and Simulink, workflows like the one described by Francesco allow to fully exploit a wide range of features:

  • Advanced Analysis: MATLAB and Simulink control design and signal processing tools allow for a sophisticated analysis of circuit behavior.
  • Digital Filter Design: MATLAB discretization, system inversion, and signal processing capabilities facilitate the design of digital filters, for instance, to compensate for analog behaviors.
  • Integration with Logic Simulators: MATLAB and Simulink models can be exported as SystemVerilog components, enabling their reuse in logic simulators and digital verification environments.
  • Reuse within Analog Simulators: As detailed in the paper, Verilog-A models can be generated from MATLAB discrete-time state-space models, allowing for reuse in analog simulators.

 

For those interested in exploring this innovative methodology further, I highly recommend reading the full paper. It offers a guide on automatically extracting symbolic state-space models and leveraging them for efficient mixed-signal IC design and verification.

 

Read the full paper on IEEEXplore

 

For more information on how MATLAB and Simulink can enhance semiconductor design and verification, visit MathWorks Semiconductor Design and Verification solutions page, or register to our upcoming Semiconductor Webinar Series.

 

Please share your thoughts and experiences in the comments below!

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