{"id":61,"date":"2009-07-25T18:23:20","date_gmt":"2009-07-25T18:23:20","guid":{"rendered":"https:\/\/blogs.mathworks.com\/seth\/2009\/07\/25\/better-bus-modeling-how-to-remove-busmux-confusion\/"},"modified":"2009-07-25T18:24:31","modified_gmt":"2009-07-25T18:24:31","slug":"better-bus-modeling-how-to-remove-busmux-confusion","status":"publish","type":"post","link":"https:\/\/blogs.mathworks.com\/simulink\/2009\/07\/25\/better-bus-modeling-how-to-remove-busmux-confusion\/","title":{"rendered":"Better Bus Modeling (How to remove Bus\/Mux confusion)"},"content":{"rendered":"

Earlier this week, Guy<\/a>\r\nand I were discussing the sometimes-strange behavior of mux and bus signals.\u00a0\r\nSometimes people find a Mux block in their model that appears to output a bus\r\nsignal.\u00a0 In this post, I will explain the underlying cause of this behavior and\r\ngive you a short Simulink history lesson.<\/p>\r\n\r\n

Don\u2019t let your eyes deceive you!<\/strong><\/p>\r\n\r\n

Most people have the correct mental model of the Mux block\r\nas a vector creator.\u00a0 When you see a Mux block, the expectation is it outputs a\r\nwide signal (a vector).\u00a0 Here is a very simple model that does not<\/em>\r\nbehave this way.<\/p>\r\n\r\n

\"A<\/p>\r\n\r\n

This is actually a misleading.\u00a0 Mux blocks are virtual, so\r\nthey don\u2019t actually do anything during the simulation.\u00a0 Virtual Bus signals are\r\nsimilar to Mux blocks. \u00a0The Terminator is also virtual (it doesn\u2019t update,\r\ncompute outputs, etc.)\u00a0 When you consider those observations, all that is left\r\nare the ports and the Gain block.<\/p>\r\n\r\n

Sometimes a Mux block can output a bus signal.\u00a0 Huh?\u00a0 But,\r\nI thought the Mux block created a vector!<\/em><\/p>\r\n\r\n

The Mux Used to Create Bus Signals<\/strong><\/p>\r\n\r\n

A long time ago, in a much earlier version of Simulink, the\r\nBus Selector was introduced to allow users to select signals by name from a\r\nbundle of signals.\u00a0 The Mux block created this \u201cbundle\u201d of signals.<\/em>\u00a0 Simulink\r\nonly supported vectors (no matrices), so there was very little difference\r\nbetween a virtual muxed signal and a virtual bus signal.<\/p>\r\n\r\n

Soon after the introduction of the Bus Selector, developers\r\nadded the Bus Creator to reduce confusion about the mixed meaning of Mux\r\nblocks.\u00a0 At the time, the Bus Creator still behaved much like a Mux block and\r\nactually shared code with the Mux block.\u00a0 For compatibility reasons, the Mux block\r\nhad to continue supporting the creation of bus signals.<\/p>\r\n\r\n

Over time, Simulink semantics changed and the difference\r\nbetween bus signals and vectors got more significant.\u00a0 In R14 Simulink (circa\r\n2004), there were edge cases where the mixing of mux and bus caused problems.\u00a0\r\nSimulink developers wanted to migrate to a clean bus modeling behavior, but it would\r\nbreak <\/strong>legacy models that depended on the Mux block to create bus\r\nsignals.\u00a0 It was too dramatic a change to switch to the new and improved\r\nbehavior without giving modelers a way to opt-in.\u00a0 How did they do it?<\/p>\r\n\r\n

The Solution: Error Checking<\/strong><\/p>\r\n\r\n

The Connectivity Diagnostic -> Mux blocks used to\r\ncreate bus signals<\/em> was introduced to control this behavior.\u00a0 When a Mux\r\nblock creates a bus, Simulink now handles it in one of three ways.<\/p>\r\n\r\n

\"The<\/p>\r\n\r\n

This diagnostic can be set to none<\/em>, warning<\/em>,\r\nor error<\/em>.<\/p>\r\n\r\n

none<\/em> \u2013 This is the historical behavior of the Mux\r\nblock, creating vector signals AND bus signals when needed.\u00a0 Full backward\r\ncompatibility, plus the edge cases I talked about before.<\/p>\r\n\r\n

warning<\/em> \u2013 This is the historical behavior of the Mux\r\nblock, plus a post compile check to find Mux blocks that might<\/em> be used a\r\nbus creators.\u00a0 Simulink reports warnings it finds one.<\/p>\r\n\r\n

error<\/em> \u2013 This is the clean bus modeling behavior the\r\ndevelopers implemented. If a Mux block is used to create a signal that is\r\ntreated like a bus, an error stops the update diagram process.<\/p>\r\n\r\n

Because this diagnostic asserts that it is an error to use a\r\nMux block as a bus creator, Simulink assumes that only Bus Creators make bus\r\nsignals.\u00a0 This assumption resolved the edge cases and made the clean bus\r\nmodeling behavior possible.\u00a0 Because this is a diagnostic and the default is warning<\/em>,\r\nlegacy models still worked when people upgraded.\u00a0 Some issues were actually\r\nresolved by changing the diagnostic to error.<\/p>\r\n\r\n

How to Fix the Warning\/Errror<\/strong><\/p>\r\n\r\n

The warning and error messages provide some direction on how\r\nto resolve the problem.\u00a0 There are even commands you can call to help fix your\r\nmodel.\u00a0 This is an example of a model that produces a warning about mixing mux\r\nand bus.<\/p>\r\n\r\n

\"A\u00a0<\/p>\r\n\r\n

Warning: The block diagram 'muxORbusWarning'\r\nimproperly uses 1 Mux blocks as Bus Creators. This can lead to modeling errors\r\n(see the Mux block documentation for more information). To avoid such errors,\r\nreplace the Mux blocks with Bus creator blocks and enable strict bus modeling\r\n(see slreplace_mux command). To enable strict bus modeling, set the 'Mux blocks\r\nused to create bus signals' option to 'error' in the Connectivity pane of the\r\nDiagnostics page in the Configuration Parameters Dialog.<\/em><\/p>\r\n\r\n

Don't stop there!<\/strong><\/p>\r\n\r\n

For similar reasons you should also set Bus signal\r\ntreated as vector<\/em> to error.<\/p>\r\n\r\n

Fixing the original model<\/strong><\/p>\r\n\r\n

When the original model uses strict bus mode, the signal\r\ndraws as a vector signal instead of a bus.<\/p>\r\n\r\n

\"Mux<\/p>\r\n\r\n

Now it\u2019s your turn<\/strong><\/p>\r\n\r\n

The take away from this post is that you should set these\r\ndiagnostics to error to get the BEST mux\/bus behavior.\u00a0 Do you model in strict\r\nbus mode?\u00a0 Tell me about it and leave a comment here<\/a>.<\/p>","protected":false},"excerpt":{"rendered":"

Earlier this week, Guy\r\nand I were discussing the sometimes-strange behavior of mux and bus signals.\u00a0\r\nSometimes people find a Mux block in their model that appears to output a bus\r\nsignal.\u00a0 In this... read more >><\/a><\/p>","protected":false},"author":40,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[7,11,33],"tags":[12,13,441],"_links":{"self":[{"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/posts\/61"}],"collection":[{"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/users\/40"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/comments?post=61"}],"version-history":[{"count":0,"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/posts\/61\/revisions"}],"wp:attachment":[{"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/media?parent=61"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/categories?post=61"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.mathworks.com\/simulink\/wp-json\/wp\/v2\/tags?post=61"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}