The word agent comes from the Latin verb agere, meaning “to do” or “to act.” In common parlance, an agent acts on behalf of another person or a group. However, the definition I find most useful is rooted in agency: the capacity to act or exert power. In that sense, Agentic AI is about giving AI delegated agency—enabling it to pursue goals, plan across steps, reason through tasks, use memory, and call external tools to execute workflows with increasing autonomy.

But how does one put AI agents to work effectively in engineering? Engineering is built on foundations of accuracy and determinism, both of which are things that Generative AI and LLMs regularly struggle with. Agentic AI offers another approach: enlist engineering tools with these key capabilities. Simulink has been used as a trusted design and simulation environment for engineering applications for decades and comes with the added advantage that it can clearly show system architecture and help engineers understand system complexity – the kind of transparency that Generative AI could also benefit from.

With my own background as a semiconductor designer, I wanted to see how combining Simulink with Agentic AI could accelerate semiconductor—particularly AMS—design and verification. Simulink is particularly well suited for modelling hardware components as it accurately estimates the time-varying effects and natively combines continuous-analogue and discrete-time digital behaviour, often present in mixed-signal designs.

Here, I document my efforts and experiences and share my thoughts on how Agentic AI can accelerate semiconductor design workflows, specifically Analog design.

Interested to learn more?  visit our MathWorks Solutions for Semiconductors Site

The Framework: Simulink Agentic Toolkit (SATK)*

The Simulink® Agentic Toolkit lets Simulink users of varied experience levels leverage the power of LLMs with AI Agents by giving your AI the knowledge and context to read, build, edit, and test Simulink® models using Model-Based Design best practices. It connects agents to Simulink through the MATLAB MCP Server, giving them the ability (tools) and the knowledge (skills) to work with Simulink models effectively.

*If you are unfamiliar with the Model Context Protocol and how it’s applied to the Agentic AI framework, please refer to Agentic AI 101

Mental Model: A simple but useful framework of Agentic AI

Reimagining Analog & Mixed Signal design as a Multivariate Optimization problem

Any Analog designer who has graduated from university in this century will be familiar with Bezad Razavi’s work on Analog design. Below is a visual representation of what trade-offs and design choices AMS practitioners go through for a typical design:

Tradeoff’s abound: The Analog Design Octogen

To further complicate things, we have to consider the fabrication process of sub-micron technology nodes, where second- and third-order effects exacerbate complexity and permutations quickly explode. Dealing with this level of variability can lead to suboptimal design choices – and often a splitting headache.

Let’s consider this by way of an example: something that most Analog and Mixed-Signal designers are familiar with, a Phase-Locked Loop ( PLL).

A Phase-Locked Loop is simply an electronic feedback control circuit that generates an output signal with a phase and frequency matched to an input reference signal. This is commonly used to generate a higher-frequency clock from a lower-frequency reference, with the generated higher frequency used to clock the rest of the on-chip circuitry.

If you were to scoff at this description of a PLL with “that sounds easy”, then let me add some more flavour. A PLL consists of a Phase Frequency Detector (PFD), Charge Pump, Loop filter, Voltage Controlled Oscillator (VCO), and a bank of dividers; overall, it has many crossovers between the digital and analog domains. All these sub-circuits have issues with non-linearity, current mismatch, dead zone, device noise, jitter and phase errors, not to mention the Process/Voltage/Temperature (PVT) variation effects and supply dependence. Optimizing for all these parameters within the constraints of Power, Performance, and Area (PPA) can be a challenging endeavour even for seasoned AMS professionals.

For a given PLL specification, many solutions are possible. To navigate a large solution space and systematically investigate or better understand design trade-offs, you can deploy a Design of Experiments (DoE) methodology. Simulink’s DOE capabilities and the power of Agentic AI can significantly expedite these iterations if the engineer is clear on which trade-offs are acceptable.

The Iterative Engine: The true power of Agentic AI

In the example below, I’m roleplaying as a novice Simulink user, and I have used SATK to give the agent access to the installed Simulink capabilities. This helped prevent the AI coding agent from taking wrong turns or wasting time (and tokens) on extra steps that experienced Simulink users would skip.

User Prompt for Codex:

Design an integer-N PLL with the following architecture: PFD, CP, filter, VCO, dividers. Use the following parameters: input frequency of 10 MHz, output frequency of 100 MHz. Don’t assume anything else and ask me further questions

No Assumptions: The corresponding output from the LLM based on my exact prompt

Watching the AI Agent build the PLL model in front of my eyes, assembling the blocks and connecting them together, determining parameters and simulating them, checking results and then iterating on the design – was nothing short of magical

A sprinkling of Agentic AI

After a few minutes and a few iterations on the specifications, the LLM built and simulated a PLL with a 10 MHz input and a 100 MHz output as I had requested. However, the capacitor used for this simulation was 1060 pF (1.06 nF), which I know from my own experience would overshadow the rest of the active circuitry. To optimize the design for area, even before transistor-level simulations, we must iterate again and resize the loop-filter capacitor.

The AI-generated design was correct according to the block specifications. Nonetheless, a 30% reduction in capacitor area is the difference between a getting the IP being selected for a design or getting relegated to a “Silicon-proven, Never used” status. I completed the design loop with the some polite words to the Agentic AI to redesign the PLL with a 700pF loop capacitor.

Caveat Emptor: A Working PLL model, with steep real estate cost

A graphical simulation in Simulink helps me, as a subject-matter expert, identify and fix these issues and validate what my AI Agent has produced.

PLL Top Level: The model created by the LLM, refactored to create a classic PLL design

Once we were confident in the architecture, I asked the LLM to dive deeper and create a MATLAB App where I could investigate the trade-offs between charge-pump current, VCO gain, and lock time. I further instructed the LLM that the “PLL Simulation App” should run the Simulink model every time any parameter changes, and list the critical measurement parameters for me to monitor.

The first cut outcome is a simple but useful dashboard as shown below.

DOE App: A “Design of Experiments” dashboard which allows us to see the outcome of our design choices

It turns out Agentic AI is also very good at building Apps with User Interfaces in MATLAB, achieving in a couple of minutes what would previously have taken me several hours. And here the productivity gain is especially notable, as an app like this is not the core design work, but an ancillary tool – and so building the app itself is direct overhead cost that can be significantly cut.

In conclusion: Agentic AI should be considered as a colleague who is proficient with MATLAB and Simulink and extremely fast. That said, this AI colleague is not a subject-matter expert and will only do what you specifically ask it to do. As the subject-matter expert, You are essential to the process to ensure a good outcome – and in the end this is an outcome that you must own and be responsible for. But the AI Agent does offer the prospect of focusing your time on the parts of the design where you are really providing value as an SME, and letting the AI Agent race through the rest.

Where do you see the biggest opportunity for Agentic AI in semiconductor design? We’d love to hear about your experiences, challenges, and lessons learned as AI becomes part of the engineering workflow. Share your thoughts in the comments below.

Interested to learn more?  visit our MathWorks Solutions for Semiconductors Site