Guy and Seth on Simulink

August 2nd, 2011

Wouldn't it be great if you could analyze a Simulink model and certify that it will never encounter design errors like divisions by zero and overflows? Since MATLAB R2011a, this is possible!

This week, my friend Nishaat Vasi introduces this new feature of Simulink Design Verifier

Detecting Design Errors with Simulink Design Verifier

Imagine driving a new prototype of a car on a test track at 100mph when a division by zero error in the embedded design causes an unwarranted transmission shift to first gear. Even a car enthusiast would not want to be the test-track driver in such a scenario! Such errors in design logic and math operations can be easily detected in your Simulink models without requiring extensive tests or simulation runs.

Consider a small section of a controller model that has an input bus which I defined in the MATLAB workspace:

This model simulates fine for my set of inputs in the InBus declaration, but I wanted to be sure that it will not cause any dynamic execution errors. I used the new Detecting Design Errors option of the Simulink Design Verifier as follows:

The tool highlights the analysis results on the model making it much easier to debug potential issues:

For each block with an error (red), Simulink Design Verifier calculates signal-range boundaries and generates a test vector that reproduces the error in simulation. Using this test case made it easy for me to identify what set of inputs cause an error and engineer a defensive mechanism to avoid this scenario. As you may notice, green highlighting indicates that the block does not produce a design violation. Design errors detected include dead logic, integer overflow, division by zero, and violations of design properties and assertions. This information can then be used to either improve the design and its requirements or guide the simulation for debugging and validation.

To learn more about the technology, you can visit How does Simulink Design Verifier identify design errors? or check out the Product Overview video:

This new R2011a feature could save you huge amounts of time, effort, and money in debugging design errors – even before running a simulation!

Now it's your turn

What do you think of the Design Error Detection feature? Did you encounter such design error in the past? Leave us a comment here.

By Guy Rouleau

18:08 UTC | Posted in Guest Blogger, Verification & Validation | Permalink | 3 Comments »

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3 Responses to “Detecting Divide by Zero Errors”

1. KE replied on April 13th, 2012 at 11:10 UTC :
   

   What is the standard approach to eliminating a divide by zero error? I am getting it at the first time step, yet setting an initial condition does not eliminate it.

2. Guy Rouleau replied on April 13th, 2012 at 13:02 UTC :
   

   @KE, I am not sure if there is one “standard” option. I guess this depends on your application. For example, I have seen:

   - Use one of the technique described here to use an alternate algorithm when the value to be divided is close or equal to 0.

   - If you are getting this at the first time step, maybe it would be possible to use different initial conditions? (not the IC block, but initial conditions in Delays and Integrators)

3. KE replied on April 17th, 2012 at 15:00 UTC :
   

   I ended up using the approach in the link below, but thanks for the head’s up (I did try the IC and it was unsuccessful as you indicated).
   http://www.mathworks.com/support/solutions/en/data/1-F5WMK3/index.html?product=ML&solution=1-F5WMK3

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<pre class="code">
a = magic(3);
sum(a)
</pre>

These postings are the author's and don't necessarily represent the opinions of MathWorks.