Guy on Simulink

Simulink & Model-Based Design

What’s New in R2017a! 8

Posted by Guy Rouleau,

MATLAB R2017a is now available for download. For this first post about R2017a, I want to highlight features that will help you creating models more efficiently.

Simplified Subsystem Bus Interfaces

I often receive large models from users where subsystems and buses are arranged like the following. By using a wrapper virtual subsystem, this pattern helps to avoid line cluttering.

Bus before

In R2017a, thanks to the new bus element ports, your Subsystems can now look like this:

Bus R2017a

If you want to convert your existing models to this new semantics, we also added a functionality to do the conversion automatically:

Bus Conversion

Improved Parameterization of Referenced Models

For those of you who need to pass arguments to referenced models, you will notice the new Argument column in the Model Explorer when creating new variables in the model workspace:

Model arguments

When referencing the model, the dialog of the Model block will list the variables marked as Arguments and allow you to specify their value. For those of you with many arguments, notice that the table is searchable and sortable.

Model arguments values

Automatic Port Creation

In R2017a, you can simply drag a signal line close to a block and a new port will automatically appear. The best way to describe this feature is to see it in action:

Automatic Port Creation

Format Painter

Easily apply the formatting of one block to other blocks using the format painter:

Format Painter

Now it's your turn

Those are some of the features added in R2017a to help you editing model more efficiently. There are many other exciting new features I will be blogging about soon.

Look at the release notes, and let us know in the comments below what is your favorite new feature, or which one you would like to read about on this blog.

8 CommentsOldest to Newest

Scott Thomson replied on : 1 of 8

Automatic port creation, particularly for stateflow charts, looks amazing!

Do you know if the new bus element blocks are supported by embedded coder and coder inspector?

Teresa Hubscher-Younger replied on : 2 of 8

Thanks for saying Automatic port creation looks amazing!

Bus Element Ports are supported by embedded coder, but are not supported by code inspector right now, I believe.

Saurabh Mahapatra replied on : 3 of 8

My favorite feature is Simulink Cache. Great enhancement for large scale models. Best wishes.

Charlie Harrison replied on : 4 of 8

I particularly love both the automatic port creation and the subsystem bus interface. This new way of directly accessing bussed signals within a subsystem I have to say is going to be highly applicable for our models and will cut down on a bunch of redundant layers of modeling.

Michael Corbett replied on : 5 of 8

For the “Simplified Subsystem Bus Interfaces” feature, is it possible to accomplish Bus Assignment type behavior rather than Bus Creator type behavior? For example, I have a large bus which enters a subsystem as shown in Guy’s example. Also similarly, calculations occur in the deepest subsystem. However in my case the middle layer is different. Rather than creating a new bus for the results x and y and leaving the inputs a, b, and c behind, I assign the results of the calculations to values on the existing bus (i.e. the output bus contains a, b, c, x, y, and any other items that were on the original input bus but weren’t needed in this particular calculation). Another question along the same lines…can this feature make use of bus objects (either manually or automatically)?

Teresa Hubscher-Younger replied on : 6 of 8

Hi Michael,
For the bus assignment behavior, it sounds like what you are asking for is overlapping writes or a type of bus merging and appending behavior? Is this correct? If so, I don’t think it’s supported. You will need Bus Assignment blocks to do this, if I understand this correctly.

In terms of bus objects, only bus element ports that select elements of a non-virtual bus are supported. Using bus objects to define buses at the interfaces is currently not supported. You can work around this by inserting a Signal Conversion or Signal Specification block at the output of the Subsystem and specify the bus object there.

Michael Corbett replied on : 7 of 8

Hi Teresa,

Thanks for the response. Basically, I define all my signals in a big hierarchical bus object using scripts that run in a model load callback. Then I pass that that single bus from one subsystem to the next to the next. Within each subsystem, various bus elements are read from the bus and used in math. Other bus elements are written and then the same bus object leaves that subsystem. It sounds like the feature is heading in the right direction for me, but isn’t ready for my use in its current form.

Teresa Hubscher-Younger replied on : 8 of 8

Michael, Thank you for giving us details about your workflow. It’s very helpful for us to know as we develop features.

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